Power domain aware insertion methods and designs for testing and repairing memory

ABSTRACT

Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example embodiments, each power domain of the integrated circuit, and the memories included therein, are associated with dedicated test data register (TDR) set and instruction set. Each instruction set causes memory test logic circuitry in the integrated circuit to test the memories included in the corresponding power domain in parallel. Once testing of memories within a particular power domain is over, the test circuitry tests memories belonging to another power domain in parallel, and so on.

TECHNICAL FIELD

The subject matter disclosed herein relates to design and analysis ofelectrical circuits. In particular, example embodiments relate to powerdomain aware insertion methods and designs for testing and repairingmemory.

BACKGROUND

Traditional approaches to testing, diagnosing and repairing on-chipmemories involve a testing architecture that includes a 16-state statemachine and at least four input/output (I/O) pins in the design. Thememories are tested using memory built-in-self-test approach (MBIST),which utilizes a number of algorithms to test the memories. To ensurethat no defects are present in the design, large number of algorithmsare run to test the memories, which results in very long test-time for achip.

In some instances, memories may be tested in parallel to reduce testtime. However, with the abundance of memories present on a current chip,running all of them in parallel causes the chip to consume substantialamounts of power, which may damage or destroy the chip. Moreover, alarge number of chip designs have multiple power domains out of whichnot all the domains are active at the same time. If memories are presentin different power domains then a lot of extra isolation and/orretention logic is required to test these memories properly.

Some further approaches involve testing memories in a group in parallel,but in series with another group. This approach attempts to balance thetest-time and power, but has a number of limitations. For example, withthis approach, all the memories are still associated with a single setof test-data-registers (TDRs) included in the testing architecture. EachTDR in a set of TDRs acts as a scan chain and has an associatedinstruction. The loading and unloading of these TDRs (based onassociated instructions) is performed at the frequency of the test clockinput (TCK), which is relatively small, so it takes a long time to loadand unload the TDRs. Furthermore, the loading and unloading of theseTDRs is done quite frequently to schedule the memories, observe theresults, and take appropriate actions, thereby increasing the test-time.

Moreover, if a chip has memories in different power domains then thereexists no proper method to test the memories. For example, the memorytesting logic may be inserted into the proper power domain, but when thememory testing logic is stitched in one set of TDRs crossing through allthe power domains, state retention and isolation logic is required tomake that work which is unnecessary overhead in terms of hardware.

BRIEF DESCRIPTION OF THE DRAWINGS

Various ones of the appended drawings merely illustrate exampleembodiments of the present inventive subject matter and cannot beconsidered as limiting its scope.

FIG. 1 is a block diagram illustrating a high level architecture of anintegrated circuit, according to some example embodiments.

FIG. 2 is block diagram illustrating functional components of a memorytest logic circuitry, which is provided as part of the integratedcircuit, according to some example embodiments.

FIG. 3 is a flow chart illustrating a method for inserting power domainaware memory test logic into an integrated circuit, according to someexample embodiments.

FIG. 4 is a flow chart illustrating a method for inserting power domainaware memory test logic into an integrated circuit, according to somealternative example embodiments.

FIG. 5 is a flow chart illustrating a method for testing memory in aparticular power domain of the integrated circuit, according to somealternative example embodiments.

DETAILED DESCRIPTION

Reference will now be made in detail to specific example embodiments forcarrying out the inventive subject matter. Examples of these specificembodiments are illustrated in the accompanying drawings, and specificdetails are set forth in the following description in order to provide athorough understanding of the subject matter. It will be understood thatthese examples are not intended to limit the scope of the claims to theillustrated embodiments. On the contrary, they are intended to coversuch alternatives, modifications, and equivalents as may be includedwithin the scope of the disclosure.

Aspects of the present disclosure involve insertion of power domainaware memory testing logic into integrated circuit designs to enableefficient testing of the memories embedded therein. In exampleembodiments, memories present in different power domains are associatedwith different test data register (TDR) sets and different instructionsets, and only one instruction set is active at a time. In this manner,a unique instruction set for testing the memories of a power domain isprovided for each power domain included in the integrated circuit.Memories belonging to one domain may be tested in parallel. Once theirtesting is over, memories belonging to another domain may be tested inparallel, and so on. By providing the ability to test memoriesassociated with a particular domain (or instruction set) in parallel,these example embodiments achieve a shorter testing run-time. It shallbe appreciated, however, that the methodologies disclosed herein are notlimited to testing memories belonging to a single domain in parallel,and in other embodiments, memories present in a single domain may betested in series or in various combinations of parallel and series.Further, the methodologies disclosed herein are not limited to testingmemories using a different instruction set for each power domain, and inother embodiments, a single instruction set may be assigned to multipledifferent power domains.

Further, because only one instruction set can be active at any giventime, the memory testing logic and corresponding TDR of each powerdomain are isolated from other power domains. Thus, no additionalisolation or retention logic is needed to test the memories belonging toa particular domain, and the area overhead associated with memorytesting is thereby reduced. Moreover, because only one instruction setcan be active at any given time, only those memories that are associatedwith a particular instruction set can be tested in parallel, and as aresult, this design achieves the technical effect of reducing the peakpower consumption during testing. Additionally, the length of the TDR'sis reduced when compared to traditional approaches because memoriesbelonging to different domains have separate TDRs and, as a result, theload/unload time of the TDRs is reduced when compared to traditionalapproaches.

FIG. 1 is a block diagram illustrating a high level architecture of anintegrated circuit 100, according to some example embodiments. Those ofordinary skill in the art may also refer to the integrated circuit 100as an IC, chip, or microchip, and understand the integrated circuit 100to be an example thereof. To avoid obscuring the inventive subjectmatter with unnecessary detail, various functional components of theintegrated circuit 100 that are not germane to conveying anunderstanding of the inventive subject matter have been omitted fromFIG. 1. However, a skilled artisan will readily recognize that variousadditional functional components may be included in the integratedcircuit 100 to facilitate additional functionality that is notspecifically described herein.

As shown, the integrated circuit 100 illustrated in FIG. 1 includesthree power domains—namely, power domain 101, 102, and 103. Each of thepower domains 101-103 is a collection of cells that each have a similarlow-power behavior and control. The power domains 101-103 may beconfigured to be in communication with each other (e.g., via a bus ordirect connections) so as to allow signals (e.g., information) to bepassed between power domains or so as to allow the functional componentswith each power domain to share and access common data (e.g., storeddata or data received as input). Further, each of the power domains101-103 include, among other functional components, one or moremachine-readable data storage units known as memories (e.g.,semiconductor memory). Examples of memory types that may be included ineach of the power domains 101-103 include computer memory, read-onlymemory, volatile memory, and non-volatile memory.

The integrated circuit 100 also includes a memory test logic circuitry104 for testing the memories included in the power domains 101-103.Consistent with some embodiments, the memory test logic circuitry 104may be provided in accordance with industry standards (e.g., IEEE1149.1) and accordingly, the memory test logic circuitry 104 maycorrespond to a JTAG macro. The memory test logic circuitry 104 includesa standard interface through which test data logic and input controlsignals is communicated and uploaded by a memory testing machine(referred to hereinafter simply as a “tester”), and result data iscommunicated and downloaded by the tester. Further details of the memorytest logic circuitry 104 and its standard interface, known as a testaccess port (TAP), are discussed below, in accordance with exampleembodiments, in reference to FIG. 2.

The memory test logic circuitry 104 includes multiple instruction sets,collectively forming memory test logic, for testing, diagnosing, andrepairing the memory. Each instruction set includes multipleinstructions, each of which relates to a particular function. Morespecifically, each instruction causes the memory test logic circuitry104 to evaluate different aspects of the memory. For example, aninstruction set may include a first instruction related to productiontesting, a second instruction related to diagnostic testing, and a thirdinstruction related to repairing memory.

Each instruction set included in the memory test logic corresponds toone of the power domains 101-103 and, accordingly, the instructionsincluded in each instruction set are specifically associated withmemories in the corresponding power domain. By way of example, powerdomain 101 is associated with a first instruction set, power domain 102is associated with a second instruction set, and power domain 103 isassociated with a third instruction set. During testing, a power domainis active when the corresponding instruction set is active, and allother power domains are inactive. Thus, only one instruction set isactivate at any given time, and as such, only one power domain is activeat any given time. Moreover, all memories present in a power domain aretested in parallel.

Memories present in each of the power domains 101-103 are alsoassociated with a different isolated set of test data registers (TDR).In other words, the set of TDRs associated with one power domain isseparate and distinct from the set of TDRs associated with another powerdomain. For example, as illustrated in FIG. 1, power domain 101 isassociated with TDR set 1, power domain 102 is associated with TDR set2, and power domain 103 is associated with TDR set 3. Each set of TDRsis a machine-readable storage unit that stores a result of the executionof the instruction set on the memories of the corresponding power domainin the form of result data. Each TDR within a TDR set corresponds to aparticular instruction within an instruction set. Following the exampleform above, TDR set 1 stores a result of the execution of instructionset 1 on the memories of power domain 101, TDR set 2 stores a result ofthe execution of instruction set 2 on the memories of power domain 102,and TDR set 3 stores a result of the execution of instruction set 3 onthe memories of power domain 103. The result data stored in the TDR sets1, 2, and 3 during testing may be read by the tester via the interfaceof the memory test logic circuitry 104.

During testing of the memories included in the integrated circuit 100,only a single instruction set from the test data logic is active at atime. In this way, only memories associated with a particularinstruction (e.g., all memories included in a particular power domain)are tested in parallel. As a result, the peak power consumption of theintegrated circuit 100 during testing is reduced, and the length of theTDRs is shorter when compared to traditional methods that utilize asingle TDR set because memories belonging to different domains havetheir own dedicated TDR set.

FIG. 2 is block diagram illustrating functional components of the memorytest logic circuitry 104, which is provided as part of the integratedcircuit 100, according to some example embodiments. The memory testlogic circuitry 104 allows test instructions, collectively comprisingmemory test logic, and associated test data to be fed into a componentand subsequently allows the results of execution of the testinstructions to be read out in the form of result data. As shown, thememory test logic circuitry 104 includes a test access port (TAP) 200that provides an interface to the memory test logic circuitry 104. TheTAP 200 includes I/O pins 201-204, which are dedicated pins used withthe memory test logic. More specifically, pin 201 is referred to as thetest data input (TDI) pin, which is configured to receive a serial inputcontrol signal for test data logic (e.g., one or more instruction sets);pin 202 is referred to as the test mode select (TMS) pin, which isconfigured to receive serial input for test logic control bits; pin 203is referred to as the test clock input (TCK) pin, which is a dedicatedtest logic clock used serially to shift test instructions, test data,and control inputs on the rising edge of the clock, and serially toshift the output data on the falling edge of the clock; and pin 204 isreferred to as the test data output (TDO) pin, which is configured toprovide serial output for test instruction and result data resultingfrom the execution of the memory test logic. In some embodiments, thememory test logic circuitry 104 may further include an additional testreset (TRST) pin that may be used to reset the memory test logic.

As shown, input received by the pins 202 and 203 (e.g., TMS and TCK) isprovided as input to a TAP controller 206. The TAP controller 206 is a16-state state machine configured to receive the two control inputs(e.g., TMS 202 and TCK 203) and generate control and clock signals forthe rest of the memory test logic circuitry 104 architecture. Upon powerup, the TAP controller 206 enters a reset state, and after reset, theTAP controller 206's state changes at the rising edge of TCK 203 basedon the value of TMS 202.

Instruction sets may be received as input by the pin 201, and stored inthe instruction registers 208. More specifically, each instruction setthat may be received as input corresponds to a specific power domain(e.g., one of the power domains 101-103) of the integrated circuit 100,and instruction may be loaded serially into a dedicated register setincluded in the instruction registers 208. Once an instruction orinstruction sets has been loaded into the instruction registers 208, thememory test logic circuitry 104 is configured to respond. A subsequentinstruction may then be loaded, which then configures the memory testlogic circuitry 104 to respond to the subsequent instruction. In someinstances, test data may also be loaded, via pin 201, into the memorytest logic circuitry 104 to provide a more meaningful response. The testdata may be serially loaded into the memory test logic circuitry 104 ina similar manner to the process used previously to load the multipleinstruction sets. Execution of each instruction set results in data,referred to as result data, to be loaded into TDRs 210. Morespecifically, each instruction set corresponds to a particular isolatedTDR set, and accordingly, the result data associated with the executionof instructions from a particular instruction set are loaded into theTDR set corresponding to the particular instruction set. As an example,a first instruction set loaded into register set 1 corresponds to TDRset 1, and thus, the result data associated with the execution of thefirst instruction set is stored in the TDR set 1.

After execution, by the memory test logic circuitry 104, of each testinstruction included in a given instruction set, the results of the testcan be examined by shifting data out of the corresponding TDR set orthrough TAP controller 206. Operation of the memory test logic circuitry104 may proceed by loading and executing several further instructions ina manner similar to that described and would conclude by returning thememory test logic circuitry 104 and, in some instances, on-chip systemcircuitry to its initial state.

FIG. 3 is a flow chart illustrating a method 300 for inserting powerdomain aware memory test logic into a chip-level design (e.g., achip-level design of the integrated circuit 100), according to someexample embodiments. The method 300 may be performed by a circuitdesigner or other individual using standard circuit design and synthesistools (e.g., design and synthesis software tools). Operation 305includes accessing a first block design that does not include test datalogic. The first block design may be embodied in a data object or otherdata structure accessed from a computer-readable medium (e.g., a harddrive) in communication with the circuit design and synthesis softwaretool. The first block design includes a plurality of memories and otherfunctional components that form a portion of the chip-level design. Morespecifically, the first block design represents the logic associatedwith a first power domain in the chip-level design. For example, thefirst block design may correspond to the power domain 101 of integratedcircuit 100.

Operation 310 includes defining a first instruction set. The firstinstruction set may be defined using an appropriate command provided bythe circuit design and synthesis software tool being employed. The firstinstruction set is associated specifically with the first block designand, in this way, the instruction set is specifically associated withthe first power domain represented by the first block design. The firstinstruction set includes multiple instructions related to differentfunctions for evaluating memories present in the first power domain. Forexample, for the integrated circuit 100, the first instruction setincludes multiple instructions related to different functions forevaluating memories included in the power domain 101.

Operation 315 includes inserting memory test logic circuitry for thefirst instruction set into the first block design. As shown, the method300 includes performing the operations 305, 310, and 315 for asecond-nth block designs such that a second-nth memory test logiccircuitry are inserted into second-nth blocks for instruction setsassociated with the second-nth power domains, respectively. The resultof the execution of the operations 305, 310, and 315 for the first-nthblock designs results in a plurality of block designs with embedded testdata logic.

Operation 320 includes integrating the plurality of block designs withembedded test data logic into the chip-level design. For example, thememory test logic inserted blocks need to be connected together so thatthey can be tested from the external chip level ports (e.g., thoseprovided by the TAP 200).

Operation 325 includes specifying the plurality of instruction setsincluded in the chip-level design. The plurality of instruction setsspecified as part of operation 325 correspond to the first-nthinstruction sets defined at operation 310 as part of the block design.The plurality of instruction sets defined at operation 325 are includedas part of a test logic circuit (e.g., memory test logic circuitry 104)that is inserted into the chip-level design.

Operation 330 includes inserting the test logic circuit into thechip-level design of the integrated circuit 100. Operation 330 alsoincludes inserting memory test logic comprising the plurality ofinstruction sets into the test logic circuit. Operation 335 includesinserting memory test logic for the memories (if present at the chiplevel) and connecting the memory test logic circuitry with all insertedmemory test logic. In some instances, the chip level design may includememories that are not part of the block level designs, and the insertingof the memory test logic includes inserting the applicable memory testlogic for those memories. In some embodiments, the order of operations330 and 335 may be reversed.

The execution of method 300 results in a chip-level design havingembedded power-domain aware memory test logic. Though the method 300involves defining multiple instruction sets on different design blocksduring the block design stage (e.g., operations 305, 310, and 315) andincluding the memory test logic inserted blocks in the chip-leveldesign, in other embodiments, a single instruction set may be definedfor insertion into every block design (e.g., first-nth block designs),and further instruction sets may be defined at the chip-level design soas to associate a different instruction set with each power domain inthe chip-level design. For example, FIG. 4 is a flowchart illustrating amethod 400 for inserting power domain aware memory test logic into achip-level design (e.g., the chip-level design of the integrated circuit100), according to some example embodiments. As with the method 300, themethod 400 may be performed by a circuit designer or other individualusing standard circuit design and synthesis tools (e.g., design andsynthesis software tools).

Operation 405 includes accessing a first block design that does notinclude test data logic. The first block design may be embodied in adata object or other data structure accessed from a computer-readablemedium (e.g., a hard drive) in communication with the circuit design andsynthesis software tool. The first block design includes a plurality ofmemories and other functional components that form a portion of theintegrated circuit 100. More specifically, the first block designrepresents the logic associated with a first power domain in theintegrated circuit 100 (e.g., the power domain 101).

Operation 410 includes defining an instruction set. The instruction setmay be defined using an appropriate command provided by the circuitdesign and synthesis software tool being employed. The instruction setincludes multiple instructions related to different functions forevaluating memories.

Operation 415 includes inserting memory test logic circuitry for thegiven instruction set into the first block design. As shown, the method400 includes performing the operations 405, 410, and 415 for asecond-nth block design such that memory test logic circuitry is alsoinserted into second-nth blocks. The result of the execution of theoperations 405, 410, and 415 for the first-nth block designs results isa plurality of block designs with embedded test data logic that includesthe first instruction set.

Operation 420 includes integrating the plurality of block designs withembedded test data logic into the chip-level design. For example, thememory test logic inserted blocks need to be connected together so thatthey can be tested from the external chip level ports (e.g., thoseprovided by the TAP 200).

Operation 425 includes defining a plurality of instruction sets to beincluded in the chip-level design. Each instruction set defined duringoperation 425 is specifically associated with a particular block designand, as such, each instruction set is specifically associated with aparticular power domain of the integrated circuit.

Operation 430 includes applying the plurality of instruction sets to aparticular block design so as to associate an instruction set with itscorresponding power domain. For example, for the integrated circuit 100,a first instruction set may be applied to a first block designrepresenting the power domain 101, a second instruction set may beapplied to a second block design representing the power domain 102, anda third instruction set may be applied to a third block designrepresenting power domain 103.

Operation 435 includes inserting the memory test logic circuitry 104into the chip-level design, and inserting memory test logic comprisingthe plurality of instruction sets into the memory test logic circuitry104 inserted into the chip-level design. Operation 440 includesinserting memory test logic for the memories (if present at the chiplevel) and connecting the memory test logic circuitry with all insertedmemory test logic. In some instances, the chip level design may includememories that are not part of the block level designs, and the insertingof the memory test logic includes inserting the applicable memory testlogic for those memories. In some embodiments, the order of operations435 and 440 may be reversed. As with the method 300, execution of themethod 400 results in a chip-level design having embedded power-domainaware memory test logic.

FIG. 5 is a flow chart illustrating a method for testing memory in aparticular power domain of the integrated circuit 100, according to somealternative example embodiments. The method 500 may be embodied inmachine-readable instructions for execution by a hardware component(e.g., a processor) such that the operations of the method 500 may beperformed by a specially configured machine. In particular, theoperations of the method 500 may be performed in part or in whole by amemory testing machine and, accordingly, the method 500 is describedbelow by way of example with reference thereto. However, it shall beappreciated that the method 500 may be deployed on various otherhardware configurations.

At operation 505, the memory tester machine supplies the memory testlogic circuitry 104 with a test clock signal via the pin 203 (e.g., theTCK pin). The test clock signal is used serially to shift testinstructions, input control signals, and test data on the rising edge ofthe clock, and used serially to output result data on the falling edgeof the clock.

At operation 510, the memory tester machine provides an input controlsignal to the memory test logic circuitry 104 via the pin 201 (e.g., theTDI pin) of the TAP 200. The input control signal instructs memory testlogic circuitry 104 to execute instruction sets from the multipleinstruction sets forming the memory test logic, and to read result datafrom the applicable TDR set. Each instruction set corresponds to aparticular power domain (e.g., one of the power domains 101-103) of theintegrated circuit 100, and each instruction set has an associated TDRset that is isolated from TDR sets associated with other instructionsets. Execution of a particular instruction set causes the memory testlogic circuitry 104 to evaluate all memories belonging to the powerdomain associated with the instruction set in parallel. During executionof a particular instruction set, the power domain associated with theparticular instruction set is active while all other power domains areinactive. The result of the evaluation of the memories is output asresult data to the TDR set associated with the particular instructionset.

At operation 515, the memory tester machine reads the result data fromthe TDR set associated with execution of the instruction set(s) involvedin the input control signal. The memory tester machine reads the resultdata by serially shifting data out of the TDR set. The memory testermachine may then provide the result data to a user (e.g., as a digitalrepresentation or physical print-out) for inspection or comparison withexpected results. In some embodiments, the method 500 may be repeatedsuch that the memory test logic circuitry 104 is provided with anadditional input control signal instructed to execute a differentinstruction set on memories from a different power domain, and thisprocess my continue until memories in all power domains have beenevaluated.

In some instances, the input control signal may instruct the memory testlogic circuitry 104 to serially execute two or more instruction setssuch that only one instruction set is active at a time, and thus, onlyone power domain is active at a time. In this manner, the sets ofmemories included in each power domain are evaluated in series althoughall the memories of a set (e.g., all memories in a particular powerdomain) are tested in parallel.

As an example of the application of method 300, as illustrated in FIG. 1the integrated circuit 100 includes three power domains—power domains101-103, and accordingly, the memory test logic inserted into the memorytest logic circuitry 104 includes three instructions sets and three testdata register sets. Each instruction set corresponds to one of the testdata register sets. In providing the input control signal to the memorytest logic circuitry 104, the tester machine may instruct the memorytest logic circuitry 104 to execute the first instruction set and, inresponse, the memory test logic circuitry 104 evaluates the memoriesincluded in the first power domain using the first instruction set. Thefirst power domain is active during evaluation of the memories includedin the first power domain while the second and third power domainsremain inactive. The results of the evaluation of the memories includedin the first power domain are loaded into and are read from the firstTDR set, which is isolated from the second and third TDR sets. Theprocess may be similarly repeated for the second and third instructionssets associated with the second and third power domains, respectively,or the first input control signal may instruct the memory test logiccircuitry 104 to execute the three instruction sets in series.

Electronic Apparatus and System

Example embodiments may be implemented in digital electronic circuitry,in computer hardware, firmware, or software, or in combinations of them.Example embodiments may be implemented using a computer program product,for example, a computer program tangibly embodied in an informationcarrier, for example, in a machine-readable medium for execution by, orto control the operation of, data processing apparatus, for example, aprogrammable processor, a computer, or multiple computers.

A computer program can be written in any form of programming language,including compiled or interpreted languages, and it can be deployed inany form, including as a standalone program or as a module, subroutine,or other unit suitable for use in a computing environment. A computerprogram can be deployed to be executed on one computer or on multiplecomputers at one site, or distributed across multiple sites andinterconnected by a communication network.

In example embodiments, operations may be performed by one or moreprogrammable processors executing a computer program to performfunctions by operating on input data and generating output. Methodoperations can also be performed by, and apparatus of exampleembodiments may be implemented as, special purpose logic circuitry(e.g., an FPGA or an ASIC).

Language

As used herein, “machine-readable medium” means a device able to storeinstructions and data temporarily or permanently and may include, but isnot limited to, random-access memory (RAM), read-only memory (ROM),buffer memory, flash memory, optical media, magnetic media, cachememory, other types of storage (e.g., erasable programmable read-onlymemory (EEPROM)), and/or any suitable combination thereof. The term“machine-readable medium” should be taken to include a single medium ormultiple media (e.g., a centralized or distributed database, orassociated caches and servers) able to store instructions. The term“machine-readable medium” shall also be taken to include any medium, orcombination of multiple media, that is capable of storing instructionsfor execution by a machine, such that the instructions, when executed byone or more processors of the machine, cause the machine to perform anyone or more of the methodologies described herein. Accordingly, a“machine-readable medium” refers to a single storage apparatus ordevice, as well as “cloud-based” storage systems or storage networksthat include multiple storage apparatus or devices. The term“machine-readable medium” excludes signals per se.

Furthermore, the “machine-readable medium” is non-transitory in that itdoes not embody a propagating signal. However, labeling the tangiblemachine-readable medium as “non-transitory” should not be construed tomean that the medium is incapable of movement—the medium should beconsidered as being transportable from one real-world location toanother. Additionally, since the machine-readable medium is tangible,the medium may be considered to be a machine-readable device.

The various operations of example methods described herein may beperformed, at least partially, by one or more processors that aretemporarily configured (e.g., by software) or permanently configured toperform the relevant operations. Similarly, the methods described hereinmay be at least partially processor-implemented. For example, at leastsome of the operations of a method may be performed by one or moreprocessors. The performance of certain of the operations may bedistributed among the one or more processors, not only residing within asingle machine, but deployed across a number of machines. In someexample embodiments, the processor or processors may be located in asingle location (e.g., within a home environment, an office environment,or a server farm), while in other embodiments the processors may bedistributed across a number of locations.

Although the embodiments of the present disclosure have been describedwith reference to specific example embodiments, it will be evident thatvarious modifications and changes may be made to these embodimentswithout departing from the broader scope of the inventive subjectmatter. Accordingly, the specification and drawings are to be regardedin an illustrative rather than a restrictive sense. The accompanyingdrawings that form a part hereof show, by way of illustration, and notof limitation, specific embodiments in which the subject matter may bepracticed. The embodiments illustrated are described in sufficientdetail to enable those skilled in the art to practice the teachingsdisclosed herein. Other embodiments may be used and derived therefrom,such that structural and logical substitutions and changes may be madewithout departing from the scope of this disclosure. This DetailedDescription, therefore, is not to be taken in a limiting sense, and thescope of various embodiments is defined only by the appended claims,along with the full range of equivalents to which such claims areentitled.

Such embodiments of the inventive subject matter may be referred toherein, individually and/or collectively, by the term “invention” merelyfor convenience and without intending to voluntarily limit the scope ofthis application to any single invention or inventive concept if morethan one is in fact disclosed. Thus, although specific embodiments havebeen illustrated and described herein, it should be appreciated that anyarrangement calculated to achieve the same purpose may be substitutedfor the specific embodiments shown. This disclosure is intended to coverany and all adaptations or variations of various embodiments.Combinations of the above embodiments, and other embodiments notspecifically described herein, will be apparent, to those of skill inthe art, upon reviewing the above description.

In this document, the terms “a” or “an” are used, as is common in patentdocuments, to include one or more than one, independent of any otherinstances or usages of “at least one” or “one or more.” In thisdocument, the term “or” is used to refer to a nonexclusive or, such that“A or B” includes “A but not B,” “B but not A,” and “A and B,” unlessotherwise indicated. In the appended claims, the terms “including” and“in which” are used as the plain-English equivalents of the respectiveterms “comprising” and “wherein.” Also, in the following claims, theterms “including” and “comprising” are open-ended; that is, a system,device, article, or process that includes elements in addition to thoselisted after such a term in a claim is still deemed to fall within thescope of that claim.

What is claimed is:
 1. A system comprising: an integrated circuitcomprising a plurality of power domains, each power domain including aplurality of memories; and a memory test logic circuitry embedded in theintegrated circuit, the memory test logic circuitry including a memorytest logic and a plurality of test data register (TDR) sets, the memorytest logic including a first instruction set associated with a firstpower domain of the integrated circuit and a second instruction setassociated with a second power domain of the integrated circuit, thefirst instruction set, when executed by the test logic circuit, causingthe memory test logic circuitry to: evaluate a first set of memoriesincluded in the first power domain, and store a first result data set ina first TDR set based on a result of the evaluation, the first TDR setcorresponding to the first power domain, and the second instruction set,when executed by the memory test logic circuitry, causing the memorytest logic circuitry to: evaluate a second set of memories included inthe second power domain, and store a second result data set in a secondTDR set based on a result of the evaluation of the second set ofmemories, the second TDR set corresponding to the second power domain ofthe integrated circuit.
 2. The system of claim 1, wherein the memorytest logic circuitry further includes a test access port (TAP)configured to receive an input control signal, the control signalinstructing the memory test logic circuitry to execute the first andsecond instruction sets.
 3. The system of claim 1, wherein the inputcontrol signal causes the test logic circuit to serially execute thefirst and second instruction sets.
 4. The system of claim 1, wherein thefirst power domain is active during execution of the first instructionset.
 5. The system of claim 4, wherein the second power domain isinactive during execution of the first instruction set.
 6. The system ofclaim 1, wherein the first instruction set causes the first set ofmemories to be evaluated in parallel.
 7. The system of claim 1, whereinthe first TDR set associated with the first power domain is isolatedfrom the second TDR set associated with the second power domain.
 8. Thesystem of claim 1, wherein the test data logic further includes a thirdinstruction set associated with a third power domain, the thirdinstruction set, when executed by the memory test logic circuitry,causes the test data logic circuitry to perform operations comprising:evaluate a third set of memories included in the third power domain, andstore a third test data set in a third test data register based on aresult of the evaluation of the third set of memories, the third testdata register corresponding to the third power domain of the integratedcircuit.
 9. A method comprising: providing, using one or moreprocessors, a input control signal to a memory test logic circuitry ofan integrated circuit, the integrated circuit including a plurality ofpower domains, the input control signal causing the memory test logiccircuitry to execute a memory test logic included in the memory testlogic circuitry, the memory test logic including a first instruction setassociated with a first power domain of the integrated circuit and asecond instruction set associated with a second power domain of theintegrated circuit, the first instruction set, when executed by thememory test logic circuitry, causing the memory test logic circuitry to:evaluate a first set of memories included in the first power domain, andstore a first result data set in a first TDR set based on a result ofthe evaluation, the first TDR set corresponding to the first powerdomain, and the second instruction set, when executed by the memory testlogic circuitry, causing the memory test logic circuitry to: evaluate asecond set of memories included in the second power domain, and store asecond result data set in a second TDR set based on a result of theevaluation of the second set of memories, the second TDR setcorresponding to the second power domain of the integrated circuit. 10.The method of claim 9, further comprising: reading, via the test accessport, the first set of result data from the first test data register;and reading, via the test access port, the second set of result datafrom the second test data register.
 11. The method of claim 9, whereinthe input control signal causes the memory test logic circuitry toserially execute the first and second instruction sets.
 12. The methodof claim 11, wherein the test logic circuitry serially executing thefirst and second instructions sets causes the memory test logiccircuitry to evaluate the first and second set of memories in series.13. The method of claim 9, herein the first power domain is activeduring execution of the first instruction set.
 14. The method of claim13, wherein the second power domain is inactive during execution of thefirst instruction set.
 15. The method of claim 9, wherein the firstinstruction set causes memories within the first set of memories to beevaluated in parallel.
 16. The method of claim 13, wherein the first TDRset associated with the first power domain is isolated from the secondTDR set associated with the second power domain.
 17. The method of claim9, wherein the test logic further includes a third instruction setassociated with a third power domain, the third instruction set, whenexecuted by the memory test logic circuitry, causes the memory testlogic circuitry to perform operations comprising: evaluate a third setof memories included in the third power domain, and a third test dataset in a third test data register based on a result of the evaluation ofthe second set of memories, the second test data register correspondingto the second power domain of the integrated circuit.
 18. A methodcomprising: defining, using one or more processors of a machine, amemory test logic including a first instruction set associated with afirst power domain of an integrated circuit and a second instruction setassociated with a second power domain of the integrated circuit, theintegrated circuit including a memory test logic circuitry, the firstinstruction set, when executed by the memory test logic circuitry,causing the memory test logic circuitry to: evaluate a first set ofmemories included in the first power domain, and store a first resultdata set in a first test data register (TDR) set based on a result ofthe evaluation, the first TDR set corresponding to the first powerdomain, and the second instruction set, when executed by the memory testlogic circuitry, causing the memory test logic circuitry to: evaluate asecond set of memories included in the second power domain, and store asecond result data set in a second TDR set based on a result of theevaluation of the second set of memories, the second TDR setcorresponding to the second power domain of the integrated circuit; andinserting the memory test logic into the memory test logic circuitry ofthe integrated circuit.
 19. The method of claim 18, wherein the memorytest logic circuitry serially executes the first and second instructionsets such that the memory test logic circuitry evaluates the first andsecond set of memories in series.
 20. The method of claim 18, whereinthe first and second TDR sets are separate and distinct.